The present invention relates generally to selective coupling of semiconductor devices and in particular to methods and facilitating circuitry to permit selective coupling of multiple storage cells to improve memory device characteristics or circumvent memory device defects.
Many electronic systems include a memory device, such as a Dynamic Random Access Memory (DRAM), to store data. A typical DRAM includes an array of memory cells. Each memory cell includes a storage capacitor that stores the data in the cell and an access transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit and is usually either a high voltage, logic 1, or a low voltage, logic 0.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as digit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line. Thus, each such memory cell is associated with two digit lines, digit and digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, and memory cells are generally associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to a word line or row decoder and to a digit line or column decoder. The row decoder activates a word line in response to the word line address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a digit line pair in response to the digit line address. For a read operation, the data corresponding to the selected memory cell is sensed, and the data and its complement are each latched to one digit line of the digit line pair. The column decoder further selects the digit line containing the data corresponding to the addressed memory cell for output.
The ability to sense the data stored in the storage capacitor is a critical operation of the memory device. This ability is a function of the sensitivity of the sense amplifiers to the potential differential, or cell margin, across the digit line pair. Increasing the signal-to-noise ratio thus improves the reliability of the sensing operation. Increasing the signal-to-noise ratio generally results from the increase in beta ratio, which is the ratio of the capacitance of the memory cell to the capacitance of the digit line. Increasing the beta ratio is often accomplished by isolating one half of the digit line pair from the sense amplifier.
In addition to improving reliability of the sensing operation, increases in beta ratio also permit lower power consumption in a memory device. By increasing the beta ratio, larger charge leakage is tolerable in the storage capacitor without adversely affecting the sensing operation. This permits lower refresh rates and, thus, lower power consumption.
Devices having insufficient beta ratio or excessive charge leakage are generally unsuited for their intended uses. While many causes of insufficient beta ratio and excessive charge leakage may be curable through the use of redundant devices, as is well known in the art, some causes may be global such that the redundant device also exhibits insufficient beta ratio or excessive charge leakage. Accordingly, there is a need in the art for devices capable of modifying the ratio of storage capacitance to digit line capacitance, and methods of their use.
For one embodiment, the invention includes an integrated circuit device. The integrated circuit device includes a first capacitor, a second capacitor, and a selective isolation device interposed between the first capacitor and the second capacitor.
For another embodiment, the invention includes an integrated circuit device. The integrated circuit device includes a first capacitor, a second capacitor, and a selective isolation device interposed between the first capacitor and the second capacitor, wherein the selective isolation device has a first state and a second state. The integrated circuit device further includes a device driver coupled to the selective isolation device to selectively place the selective isolation device in a state selected from the group consisting of the first state and the second state. The first capacitor and the second capacitor are electrically isolated when the selective isolation device is in the first state. The first capacitor and the second capacitor are electrically coupled when the selective isolation device is in the second state.
For a further embodiment, the invention includes a memory device. The memory device includes a first storage capacitor of a first memory cell, a second storage capacitor of a second memory cell, and a selective isolation device interposed between the first storage capacitor and the second storage capacitor.
For a still further embodiment, the invention includes a memory device. The memory device includes a first storage capacitor of a first memory cell, a second storage capacitor of a second memory cell, and a selective isolation device interposed between the first storage capacitor and the second storage capacitor, wherein the selective isolation device has a first state and a second state. The memory device further includes a device driver coupled to the selective isolation device to selectively place the selective isolation device in a state selected from the group consisting of the first state and the second state. The first storage capacitor and the second storage capacitor are electrically isolated when the selective isolation device is in the first state. The first storage capacitor and the second storage capacitor are electrically coupled when the selective isolation device is in the second state.
For yet another embodiment, the invention includes a memory device. The memory device includes a first storage capacitor of a first memory cell, a second storage capacitor of a second memory cell, a first digit line, and a second digit line. The memory device further includes a first access transistor coupled to the first storage capacitor and the first digit line for selectively coupling the first storage capacitor to the first digit line, a second access transistor coupled to the second storage capacitor and the second digit line for selectively coupling the second storage capacitor to the second digit line, and a selective isolation device interposed between the first storage capacitor and the second storage capacitor, and having a first state and a second state. The first storage capacitor and the second storage capacitor are electrically isolated when the selective isolation device is in the first state. The first storage capacitor and the second storage capacitor are electrically coupled when the selective isolation device is in the second state.
For one embodiment, the invention includes a method of operating a memory device. The method includes coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell. The method further includes coupling the first storage capacitor to a digit line while the first storage capacitor is coupled to the second storage capacitor.
For another embodiment, the invention includes a method of operating a memory device. The method includes coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell during a first period and coupling the first storage capacitor to a digit line during the first period. The method further includes electrically isolating the first storage capacitor of the first memory cell from the second storage capacitor of the second memory cell during a second period and coupling the first storage capacitor to the digit line during the second period.
For a further embodiment, the invention includes a method of operating a memory device. The method includes coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell during a first period and accessing the first memory cell during the first period. The method further includes electrically isolating the first storage capacitor of the first memory cell from the second storage capacitor of the second memory cell during a second period and accessing the first memory cell during the second period.
For yet another embodiment, the invention includes a method of operating a memory device. The method includes coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell, thereby forming a coupled capacitor pair. The method further includes selecting an access path to the coupled capacitor pair, wherein the access path is an access path coupled to the first storage capacitor or an access path coupled to the second storage capacitor, and coupling the coupled capacitor pair to a digit line through the selected access path. For a further embodiment, selecting an access path includes resolving the address by ignoring the least significant bit of the address.
For one embodiment, the invention includes a method of operating a memory device. The method includes coupling a first storage capacitor of a first memory cell to a second storage capacitor of a second memory cell during a first period, thereby forming a coupled capacitor pair. The method further includes selecting a first access path to the coupled capacitor pair, wherein the first access path is an access path coupled to the first storage capacitor or an access path coupled to the second storage capacitor, and coupling the coupled capacitor pair to a digit line through the first access path during the first period. The method still further includes electrically isolating the first storage capacitor of a first memory cell from the second storage capacitor of the second memory cell during a second period, selecting a second access path coupled to the first storage capacitor, and coupling the first storage capacitor to the digit line through the second access path during the second period.
The invention further includes apparatus and methods of varying scope.